Understanding and Minimizing Perimeter Losses of Silicon-Based Monolithic Tandem Solar Cells – A Simulation Study

Abstract

The vast majority of monolithic perovskite-silicon-based tandem cells to date is manufactured in R&D environments using small scale perovskite top cells (~1-4 cm²), typically placed on a larger silicon bottom cell. The high perimeter-to-area ratio leads to significant perimeter losses, which limit the maximum achievable efficiency and complicates loss analysis for further design optimization. An understanding of perimeter loss mechanisms and design rules for their minimization is therefore important for effectively progressing high efficient tandem solar cells in R&D. In this work we perform a 3D device simulation study of perimeter losses in an exemplary perovskite-silicon tandem solar cell. The impact of structuring the various laterally conducting layers, i.e. at the front and rear side as well as between the sub cells, on the perimeter efficiency loss is systematically investigated. We thereby identify the fundamental mechanisms of carrier transport into the perimeter, and clarify the impact of the silicon and perovskite absorber, the various laterally conducting layers, as well the electrical connection of the sub cells. We find that in each sub cell at least one carrier type must be hindered to be conducted into the perimeter. This is however complicated by the fact that this parasitic lateral transport can also be provided by “bordering” conductive layers connected via the tunnelling or recombination junction. Promising structuring variants and general design rules to achieve low perimeter losses with low structuring effort are then derived from the results. The losses are quantified to range from ~0.2 – 4%_abs for a 1 cm² top cell size, with the lowest values representing an unavoidable loss from the Si wafer conductance which is present also in champion cells with high structuring effort.